Photolithography is a common technique employed in the manufacture of semiconductor integrated circuit (IC) devices. Photolithography involves selectively exposing regions of a resist coated silicon wafer to a reticle (mask) pattern, and then developing the exposed resist in order to selectively process regions of wafer layers (e.g., regions of substrate, polysilicon, or dielectric).
An integral component of a photolithographic apparatus is a “reticle” or “mask” which includes a pattern corresponding to features at one layer in an IC design. Such a mask may typically include a transparent glass plate covered with a patterned light blocking material such as chromium. The mask may be placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed on the stepper stage may be a resist covered silicon wafer. When the radiation from the radiation source is directed onto the mask, light may pass through the glass (regions not having chromium patterns) and project onto the resist covered silicon wafer. In this manner, an image of the mask may be transferred to the resist. The resist (sometimes referred to as a “photoresist”) is provided as a thin layer of radiation-sensitive material that is spin-coated over the entire silicon wafer surface.
As light passes through the mask, the light may be refracted and scattered by the chromium edges. This may cause the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large feature sizes processed with the industry available 248 nm exposure systems (e.g., layouts with critical dimensions above about 0.35 micron), the effects may not be ignored in layouts having features smaller than about 0.18 micron. The problems become especially pronounced in IC designs having feature sizes near or below the wavelength of light used in the photolithographic process. Optical distortions commonly encountered in photolithography may include rounded corners, reduced feature widths, fusion of dense features, shifting of line segment positions, and the like. Any distorted illumination pattern may propagate to a developed resist pattern and ultimately to IC features such as polysilicon gate regions, vias in dielectrics, and the like. As a result, the IC performance may be degraded or the IC may become unusable.
To remedy this problem, a mask correction technique known as optical proximity correction (“OPC”) has been developed. OPC may involve adding regions to and/or subtracting regions from a mask design at locations chosen to overcome the distorting effects of diffraction and scattering. Manual OPC has been in existence for many years. Using manual OPC, an engineer may need to add regions using trial and error techniques until the desired pattern on the wafer is obtained. While manual OPC has been effective, as the dimensions of critical features shrink, it has become apparent that the manual approach is not time/cost effective. Therefore, a systematic way is needed to enable fast processing of large, complex chips. Generally speaking, there are currently two automated approaches to OPC: (1) rule-based OPC (use geometric rules to add corrections); and (2) model-based OPC (use lithography simulations to decide corrections). Rule-based OPC is an extension of the methods used for manual OPC. Through experiment or simulation, the corrections that should be applied in a given geometrical situation may be discovered. Then, a pattern recognition system may be used to apply the corrections wherever that geometrical situation occurs throughout the entire layout design. Model-based OPC is different from rule-based OPC in that simulation models are used to predict the wafer results and modify pattern edges on the mask to improve the simulated wafer image. The lithography simulators have traditionally used aerial image contours and cutlines for analysis of IC pattern imaging quality. Methods for simulating the aerial image, for example, as described in U.S. Pat. No. 6,171,731, are used in OPC techniques to modify the reticle pattern until the resulting simulated aerial image is within a selected tolerance from the ideal boundary of the chip design.
However, the ultimate quality of the optical proximity correction is affected not only by the refinement of the mask pattern image to be as accurate as possible to the drawn mask layout, but also by the multi mask overlay quality. Mask overlay requirements are defined by a set of design rules and device functions. The design rules account for possible mask misalignments and critical dimension (CD) errors. Violating the overlap design rules can result in failure of the IC (e.g., CMOS failure). Consequently, it is desirable to provide an effective metrology and method for measuring the multi-layer overlay quality by measuring the impact of multi-mask misalignments and post-OPC mask critical dimension (CD) variations.